The present invention relates generally to overlay measurement techniques, which are used in semiconductor manufacturing processes. More specifically, the present invention relates to analyzing overlay marks (also called overlay targets) used for measuring alignment error between different layers or different patterns on the same layer of a semiconductor wafer film stack.
In the process of manufacturing semiconductor integrated circuits, one of the critical metrology steps is overlay or misregistration measurement. The overlay measurement ideally quantifies the lateral displacement between two layers of the integrated circuit from their nominal, perfect alignment. The lateral displacement is called overlay error or misregistration (herein referred to as overlay). This metrology is typically performed by a specialized optical instrument, overlay metrology tool, on test structures located either in the so-called scribe lines on the wafer or within the area of the integrated circuit itself. These test structures are called overlay targets. The overlay metrology tool reports, as the result of each measurement, two numbers, representing the overlay in two orthogonal directions in the plane of the wafer, labeled x and y. The overlay is measured on several locations on a wafer, and on several wafers of each processing lot. The results are used primarily for two purposes. One purpose of the overlay measurements is to facilitate decisions as to whether to pass or fail a given wafer lot (known as lot dispositioning), based on the overlay values or their combinations. Another purpose is to facilitate calculating what part of these errors was due to the non-ideal alignment or other functioning of the lithography stepper or scanner, and feeding this information back to the stepper or scanner to effect corrections (known as process control). This correction is determined using a stepper analysis program, based on stepper models.
Unfortunately, the reported overlay results may not be reliable in certain situations. That is, the measured overlay measurements may be affected by other factors besides misalignment of the target. The overlay measurement may be affected by background noise associated with the measured target. In one example, background may cause an overlay error to be measured when the target is not misaligned. Systematic errors, such as asymmetry may also cause the measured overlay error to be inaccurate. In another example, a target which has significant asymmetries, combined with a significant true overlay error, may result in zero measured overlay error. Thus, the asymmetry error may go unnoticed and steps to correct process problems leading to such asymmetry may go uninitiated and adversely affect yield.
Accordingly, there is a need for improved techniques for analyzing the quality and reliability of overlay targets. There is especially a need for taking into account systematic and noise contributions as they affect the reliability of the overlay measurements.